Product Description:
The Sipeed Tang Nano 1K is a compact and cost-effective FPGA development board based on the Gowin GW1NZ-1 FPGA from the LittleBee (Small Bee) series. Designed for learning, prototyping, and digital logic experimentation, it provides a simple yet powerful platform for FPGA developers and enthusiasts.
This mini board integrates a USB-JTAG circuit for direct programming via USB, eliminating the need for external debuggers. It also includes an optional PSRAM footprint, a universal RGB display interface, and a 2.54mm pin header layout for easy hardware expansion.
Ideal for small-scale FPGA design, embedded education, or custom digital logic testing, the Tang Nano 1K delivers exceptional flexibility in a remarkably small form factor.
Key Features:
Based on Gowin GW1NZ-1 FPGA, part of the Small Bee series
Onboard USB-JTAG interface (via BL702S chip) for direct programming and debugging
Universal RGB display interface for LCD and panel connectivity
PSRAM footprint (unpopulated by default) for memory expansion
2.54mm pitch pin headers provide access to most I/O pins for easy prototyping
Supports Gowin IDE (Cloud Source Software) for HDL design, synthesis, routing, and bitstream generation
Compact and lightweight, suitable for embedded FPGA applications, education, and experimentation
Technical Specifications:
| Parameter | Specification |
|---|
| FPGA Chip | Gowin GW1NZ-1 (Small Bee Series) |
| Logic Cells | 1152 LUT4 |
| Embedded Block RAM | 72 Kbits |
| Operating Voltage | 3.3V |
| Clock Source | Onboard 24MHz oscillator |
| Programming Interface | USB-JTAG (BL702S onboard) |
| External Memory | PSRAM interface (unpopulated by default) |
| Display Interface | 24-bit RGB LCD connector |
| I/O Pins | Accessible via 2.54mm pitch headers |
| Development Environment | Gowin Cloud Source IDE |
| Dimensions | Ultra-compact mini board |
Development Environment:
The Tang Nano 1K uses Gowin Cloud Source IDE, which supports common HDL languages (Verilog/VHDL) and provides integrated tools for:
Code synthesis and implementation
Place & route and timing analysis
Bitstream file generation and FPGA configuration
Built-in IP core library for accelerated design
Example routines and starter projects are provided by Sipeed’s official GitHub and documentation, helping beginners quickly get started with FPGA development.
Applications:
FPGA learning and experimentation
Digital logic circuit design
Display control and signal processing
Educational FPGA platforms
Custom hardware and embedded development
Package Includes:
Important Note:
Avoid using JTAG pins, RECONFIG, MODE0/MODE1, and IOR5A unless properly configured. Refer to official schematics and documentation for detailed pin usage instructions.
Why Choose Tang Nano 1K?
The Sipeed Tang Nano 1K combines affordability, compact design, and ease of use, making FPGA learning and prototyping accessible to everyone. With direct USB programming, Gowin IDE support, and open resources, it’s an excellent entry-level platform for digital logic and hardware developers.
